Semiconductor manufacturers continue to reduce the size of semiconductor devices while increasing the performance and capabilities of the devices. Size reduction is typically achieved by reducing the dimensions of structures within the device and densifying the circuitry of the device. Manufacturers of memory devices are known to drive fabrication technology due to the fact that the circuitry of memory devices is inherently quite dense and repetitive. Therefore, to reduce the size of a memory device, one must rely on reducing the dimensions of structures within the device, such as transistors and capacitors. The smaller the structural dimensions, the more difficult the device is to manufacture. Thus, memory device manufacturers must overcome the fabrication difficulties, often before manufacturers of other devices.
Reducing the dimensions of memory structures, or memory cells which are comprised of a number of structures, may be accomplished in a few ways. One way is to shrink the elements of an existing structure, for example, using a 0.5 .mu.m gate width rather than a gate width of 0.8 .mu.m in a transistor. Another way of reducing the size of a memory structure is to "redesign" the structure such that it occupies less space in the semiconductor. An example of a "redesigned" structure is the SGT (surrounding gate transistor). An SGT is essentially a transistor which is built in the vertical direction as compared to transistors which have historically been planar, or built in the horizontal direction. A more detailed description of SGTs can be found in an article entitled "High Performance CMOS Surrounding Gate Transistor (SGT) for Ultra High Density LSIs," by H. Takato et al., International Electron Devices Meeting (IEDM), 1988, pp. 222-225. Another example is a trench capacitor. As with an SGT, trench capacitors take advantage of the vertical space available in a semiconductor substrate material, thus reducing the overall layout size of a semiconductor device on the substrate surface. A trench capacitor used in DRAM (dynamic random access memory) applications is discussed further in U.S. Pat. No. 4,843,025 by Morita entitled, "Method of Fabricating Trench Cell Capacitors on a Semiconductor Substrate."
Incorporating and combining the vertical structures mentioned above into a DRAM cell will significantly reduce the area of a cell to under 2 .mu.m.sup.2. Such a combination (of an SGT and a trench capacitor) has been proposed for use in 64 Mbit and 256Mbit DRAMs. An example of using an SGT combined with a trench capacitor is discussed in an article published in the proceedings of the 1989 IEDM, pp. 22-26, entitled, "A Surrounding Gate Transistor (SGT) Cell for 64/256Mbit DRAMs," by K. Sunouchi et al. This article describes a DRAM cell having an SGT and a trench capacitor which are vertically aligned along the sidewalls of one trench (the SGT being above the capacitor). By combining the transistor and capacitor into one trench, a cell size on the order of 1.2 .mu.m.sup.2 has been reported, which is considerably smaller than other cell designs which have been proposed.
Disadvantages often associated with such structures are the complexity and number of the process steps required in fabrication. For example, in order to utilize vertical space, trenches to form capacitors may be made deeper. To form deep trenches, more than one trenching step may be required. Furthermore, as the trench is formed deeper the trench also becomes narrower, resulting in manufacturing difficulties during subsequent processing. Another disadvantage with a deep, narrow trench is that the effective capacitance of the cell is reduced to below a desirable amount.